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ESMT
DDR II SDRAM
Features
JEDEC Standard VDD = 1.8V 0.1V, VDDQ = 1.8V 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle
M14D2561616A 4M x 16 Bit x 4 Banks DDR II SDRAM
Bi-directional differential data strobe (DQS, /DQS); /DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 3, 4, 5, 6 Additive Latency: 0, 1, 2, 3, 4 Burst Type : Sequential and Interleave Burst Length : 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for READ; center-aligned with data for WRITE Data mask (DM) for write masking only Off-Chip-Driver (OCD) impedance adjustment On-Die-Termination for better signal quality Special function support 50/ 75/ 150 ohm ODT High Temperature Self refresh rate enable
Auto & Self refresh Refresh cycle : 8192 cycles/64ms (7.8s refresh interval) at 0 TC +85 8192 cycles/32ms (3.9s refresh interval) at +85 TC +95
SSTL_18 interface 84-ball BGA package
Ordering Information:
PRODUCT NO. MAX FREQ VDD Data rate (CL-tRCD-tRP) DDR2-800 (5-5-5) DDR2-800 (6-6-6) DDR2-667 (5-5-5) BGA Pb-free PACKAGE COMMENTS
M14D2561616A -2.5BG M14D2561616A -3BG
400MHz 333MHz
1.8V 1.8V
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009 Revision : 1.1 1/59
ESMT
Functional Block Diagram
CLK CLK CKE Address
Mode Register & Extended Mode Register
M14D2561616A
Clock Generator
Bank D Bank C Bank B Row Decoder Row Address Buffer & Refresh Counter
Bank A
DQS, DQS
Sense Amplifier
Command Decoder
CAS WE
Data Control Circuit
Input & Output Buffer
Latch Circuit
RAS
Control Logic
CS
Column Address Buffer & Refresh Counter
DM
Column Decoder
DQ
CLK, CLK
DLL
ODT
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ESMT
Pin Arrangement 84 Ball BGA (Top View)
1 A B C D E F G H J K L M N P R
VDD VSS NC VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL
M14D2561616A
2
NC VSSQ DQ9 VSSQ NC VSSQ DQ1 VSSQ VREF CKE BA0 A10 A3 A7 A12
3
VSS UDM VDDQ DQ11 VSS
LDM
7
VSSQ
UDQS
8
UDQS
9
VDDQ DQ15 VDDQ DQ13 VDDQ DQ7 VDDQ DQ5 VDD ODT
VSSQ DQ8 VSSQ
LDQS
VDDQ DQ10 VSSQ LDQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC
VSSQ DQ0 VSSQ CLK CLK CS A0 A4 A8 NC
VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC
VDD
VSS
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ESMT
Pin Description
Pin Name Function Address inputs - Row address A0~A12 - Column address A0~A8 A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Command input Command input Command input Ground Power Bi-directional differential Data Strobe. LDQS and /LDQS are DQS for DQ0~DQ7; UDQS and /UDQS are DQS for DQ8~DQ15. On-Die-Termination. ODT is only applied to DQ0~DQ15, DM, DQS and /DQS. No connection Pin Name
M14D2561616A
Function DM is an input mask signal for write data. LDM is DM for DQ0~DQ7 and UDM is DM for DQ8~DQ15. Differential clock input Clock enable Chip select Supply Voltage for DQ Ground for DQ Reference Voltage
A0~A12, BA0,BA1
DM (LDM, UDM)
DQ0~DQ15 RAS CAS
WE
CLK, CLK CKE CS VDDQ VSSQ VREF
VSS VDD DQS, (LDQS, UDQS, ODT NC )
VDDL
Supply Voltage for DLL
VSSDL
Ground for DLL
Absolute Maximum Rating
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDL supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit output current Symbol VIN, VOUT VDD VDDL VDDQ TSTG PD IOUT Value -0.5 ~ 2.3 -1.0 ~ 2.3 -0.5 ~ 2.3 -0.5 ~ 2.3 -55 ~ +100 1 50 Unit V V V V C ( Note *) W mA
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Note *: Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Elite Semiconductor Memory Technology Inc.
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Operation Temperature Condition
Parameter Operation temperature Symbol TC Value 0 ~ +95
M14D2561616A
Unit C
Note: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. Supporting 0 to +85 with full AC and DC specifications. Supporting 0 to + 85 and being able to extend to + 95 with doubling auto-refresh commands in frequency to a 32ms period ( tREFI = 3.9s ) and higher temperature Self-Refresh entry via A7 "1" on EMRS(2).
DC Operation Condition & Specifications DC Operation Condition
(Recommended DC operating conditions) Parameter Supply voltage Supply voltage for DLL Supply voltage for output Input reference voltage Termination voltage (system) Input logic high voltage Input logic low voltage (All voltages referenced to VSS) Parameter Minimum required output pull-up under AC test load Maximum required output pull-down under AC test load Input leakage current Output leakage current Output minimum source DC current ( VDDQ(min); VOUT =1.42V ) Output minimum sink DC current ( VDDQ(min); VOUT = 0.28V ) Note: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ and VDDL track VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together. 5. Any input 0V VIN VDD; all other balls not under test = 0V. 6. 0V VOUT VDDQ; DQ and ODT disabled. 7. The DC value of VREF applied to the receiving device is expected to be set to VTT. 8. After OCD calibration to 18 at TC = 25, VDD = VDDQ = 1.8V. 9. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However, under all conditions VDDQ must be less than or equal to VDD. Symbol VOH VOL |I LI| |I LO| I OH I OL Value VTT + 0.603 VTT - 0.603 2 5 -13.4 +13.4 Unit V V uA uA mA mA Note 8 8 5 6 7, 8 7, 8 Symbol VDD VDDL VDDQ VREF VTT VIH (DC) VIL (DC) Min. 1.7 1.7 1.7 0.49 x VDDQ VREF - 0.04 VREF + 0.125 -0.3 Typ. 1.8 1.8 1.8 0.5 x VDDQ VREF Max. 1.9 1.9 1.9 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.125 Unit V V V V V V V Note 4,9 4,9 4,9 1,2,9 3,9
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DC Specifications
(IDD values are for the operation range of Voltage and Temperature) Parameter Symbol Test Condition One bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS (IDD)min; CKE is High, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING One bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS (IDD)min, tRCD = tRCD (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W All banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK (IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK (IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus input are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 15
M14D2561616A
Version -2.5 -3
Unit
Operating Current (Active - Precharge)
IDD0
70
65
mA
Operating Current (Active - Read Precharge)
IDD1
85
80
mA
Precharge Power-Down Standby Current
IDD2P
10
10
mA
Precharge Quiet Standby Current
IDD2Q
15
15
mA
Idle Standby Current IDD2N
20
20
mA
15 mA
Active Power-down Standby Current
IDD3P
12
12
Active Standby Current
IDD3N
All banks open; tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open, continuous burst Reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is the same as IDD4W; All banks open, continuous burst Writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
40
35
mA
Operation Current (Read)
IDD4R
170
145
mA
Operation Current (Write)
IDD4W
160
140
mA
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ESMT
Parameter Symbol Test Condition tCK = tCK (IDD); Refresh command every tRFC (IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self Refresh Mode; CLK and CLK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING All bank interleaving Reads, IOUT = 0mA; BL = 4, CL= CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = 1 x tCK (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during Deslects; Data pattern is the same as IDD4W; -2.5
M14D2561616A
Version -3 Unit
Auto Refresh Current
IDD5
105
100
mA
Self Refresh Current
IDD6
6
mA
Operating Current (Bank interleaving)
IDD7
240
230
mA
Note: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Input Test Condition. 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS and /DQS, IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD: LOW is defined as VIN VIL (AC) (max.). HIGH is defined as VIN VIH (AC) (min.). STABLE is defined as inputs stable at a HIGH or LOW level. FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: Address and control signal Inputs are changed between HIGH and LOW every other clock cycle (once per two clocks), and DQ (not including mask or strobe) signal inputs are changed between HIGH and LOW every other data transfer (once per clock). 6. When TC +85 , IDD6 must be derated by 80%. IDD6 will increase by this amount if TC +85 and double refresh option is still enabled. 7. AC Timing for IDD test conditions For purposes of IDD testing, the following parameters are to be utilized. -2.5 Parameter CL (IDD) tRCD (IDD) tRC (IDD) tRRD (IDD) tCK (IDD) tRAS (IDD) min. tRAS (IDD) max. tRP (IDD) tRFC (IDD) DDR2-800 (5-5-5) 5 12.5 57.5 10 2.5 45 12.5 105 DDR2-800 (6-6-6) 6 15 60 10 2.5 45 70000 15 105 15 105 -3 DDR2-667 (5-5-5) 5 15 60 10 3 45 Unit tCK ns ns ns ns ns ns ns ns
Elite Semiconductor Memory Technology Inc.
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ESMT
AC Operation Conditions & Timing Specification AC Operation Conditions
Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Differential Voltage Input Crossing Point Voltage Output Crossing Point Voltage Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) VOX(AC) 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 -2.5/ 3 Min. VREF + 0.2 VREF - 0.2 VDDQ+0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125 Max. Unit V V V V V 1 2 2
M14D2561616A
Note
Note: 1. VID(AC) specifies the input differential voltage |VTR - VCP| required for switching, where VTR is the true input signal (such as CLK,DQS) and VCP is the complementary input signal (such as CLK , ). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX / VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX / VOX(AC) is expected to track variations in VDDQ. VIX / VOX(AC) indicates the voltage at which differential input / output signals must cross.
Input / Output Capacitance
Parameter Input capacitance (A0~A12, BA0~BA1, CKE, CS , RAS , CAS , WE , ODT) Input capacitance (CLK, CLK ) DQS, & Data input/output capacitance -2.5/ 3 -2.5 -3 Symbol CIN1 CIN2 CI / O Min. 1.0 1.0 1.0 2.5 Max. 1.75 2.0 2.0 3.5 Unit Note pF pF pF 1 1 2
Input capacitance (DM) Note: 1. Capacitance delta is 0.25 pF. 2. Capacitance delta is 0.5 pF.
-2.5/ 3
CIN3
2.5
3.5
pF
2
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ESMT
AC Overshoot / Undershoot Specification
Parameter Pin Address, CKE, CS , RAS , CAS , WE , ODT, CLK, CLK , DQ, DQS,
M14D2561616A
Value -2.5 0.5 -3
Unit
Maximum peak amplitude allowed for overshoot
, DM , DM
0.66
V
Maximum peak amplitude allowed for undershoot
Address, CKE, CS , RAS , CAS , WE , ODT, CLK, CLK , DQ, DQS,
0.5
V
Maximum overshoot area above VDD
Address, CKE, CS , RAS , CAS , WE , ODT, CLK, CLK , DQ, DQS,
0.8 0.23
V-ns V-ns
, DM
0.66
Maximum undershoot area below VSS
Address, CKE, CS , RAS , CAS , WE , ODT, CLK, CLK , DQ, DQS,
0.8 0.23
V-ns V-ns
, DM
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ESMT
AC Operating Test Conditions
Parameter Input reference voltage ( VREF ) Input signal maximum peak swing ( VSWING(max.) ) Input signal minimum slew rate Input level Input timing measurement reference level Output timing measurement reference level (VOTR) Value 0.5 x VDDQ 1.0 1.0 VIH / VIL VREF 0.5 x VDDQ Unit V V V/ns V V V
M14D2561616A
Note 1 1 2,3
4
Note: 1. Input waveform timing is referenced to the input signal crossing through the VIH / VIL (AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH (AC) (min.) for rising edges and the range from VREF to VIL (AC)(max.) for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL (AC) to VIH (AC) on the positive transitions and VIH (AC) to VIL (AC) on the negative transitions. 4. The VDDQ of the device under test is reference.
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AC Timing Parameter & Specifications
Parameter CL=6 CL=5 DQ output access time from CLK/ CLK CLK high-level width CLK low-level width DQS output access time from CLK/ CLK Clock to first rising edge of DQS delay Data-in and DM setup time (to DQS) Data-in and DM hold time (to DQS) DQ and DM input pulse width (for each input) Address and Control Input setup time Address and Control Input hold time Control and Address input pulse width DQS input high pulse width DQS input low pulse width DQS falling edge to CLK rising setup time DQS falling edge from CLK rising hold time Data strobe edge to output data edge Data-out high-impedance window from CLK/ CLK Data-out low-impedance window from CLK/ CLK DQ low-impedance window from CLK/ CLK Half clock period DQ/DQS output hold time from DQS DQ hold skew factor tAC tCH (avg) tCL (avg) tDQSCK tDQSS
(base) (base)
M14D2561616A
Symbol
-2.5 Min. 2500 2500 -400 0.48 0.48 -350 -0.25 50 125 0.35 175 250 0.6 0.35 0.35 0.2 0.2 Max. 8000 8000 +400 0.52 0.52 +350 +0.25 200 tAC(max.) tAC(max.) Min. 3000 -450 0.48 0.48 -400 -0.25 100 175 0.35 200 275 0.6 0.35 0.35 0.2 0.2 -
-3 Max. 8000 +450 0.52 0.52 +400 +0.25 240 tAC(max.) tAC(max.)
Unit
Note
Clock period
tCK (avg)
ps
13
ps tCK (avg) tCK (avg) ps tCK (avg) ps ps tCK (avg) ps ps tCK (avg) tCK (avg) tCK (avg) tCK (avg) tCK (avg) ps ps
10 13 13 10
tDS
4 5
tDH
tDIPW tIS (base) tIH (base) tIPW tDQSH tDQSL tDSS tDSH tDQSQ tHZ tLZ (DQS) tLZ (DQ) tHP tQH tQHS
4 5
10
tAC(min.)
tAC(min.)
ps
10
2 x tAC(min.) Min (tCL(abs),tCH(abs)) tHP-tQHS -
tAC(max.) 300
2 x tAC(min.) Min (tCL(abs),tCH(abs)) tHP-tQHS -
tAC(max.) 340
ps ps ps ps
10 6,13
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Parameter Active to Precharge command Active to Active command (same bank) Auto Refresh row cycle time Active to Read, Write delay Precharge command period Active bank A to Active bank B command Write recovery time Write data in to Read command delay Col. address to Col. address delay Active to Auto Precharge delay Average periodic Refresh interval ( 0 TC +85 ) Average periodic Refresh interval (+85 TC +95) Write preamble Write postamble DQS Read preamble DQS Read postamble Load Mode Register / Extended Mode Register cycle time Auto Precharge write recovery + Precharge time Internal Read to Precharge command delay Exit Self Refresh to Read command Exit Self Refresh to non-Read command Exit Precharge Power-Down to any non-Read command Exit Active Power-Down to Read command Exit active power-down to Read command (slow exit / low power mode) CKE minimum pulse width (high and low pulse width) tCKE 3 3 Symbol tRAS tRC tRFC tRCD tRP tRRD tWR tWTR tCCD tRAP tREFI tREFI tWPRE tWPST tRPRE tRPST tMRD tDAL tRTP tXSRD tXSNR tXP tXARD -2.5 Min. 45 57.5 (-CL5) 60 (-CL6) 105 12.5 (-CL5) 15 (-CL6) 12.5 (-CL5) 15 (-CL6) 7.5 15 7.5 2 tRCD(min.) 0.35 0.4 0.9 0.4 2 WR+RU(tWR / tCK) +(tRP / tCK (avg)) 7.5 200 tRFC + 10 2 2 Max. 70K 7.8 3.9 0.6 1.1 0.6 Min. 45 60 105 15 15 7.5 15 7.5 2 tRCD(min.) 0.35 0.4 0.9 0.4 2 WR+RU(tWR / tCK) +(tRP / tCK (avg)) 7.5 200 tRFC + 10 2 2 -3
M14D2561616A
Unit ns ns ns ns ns ns ns ns tCK ns us us tCK (avg) tCK (avg) tCK (avg) tCK (avg) tCK tCK ns tCK ns tCK tCK 3 1 11 12 Note
Max. 70K 7.8 3.9 0.6 1.1 0.6 -
tXARDS
8 - AL
-
7 - AL
-
tCK
2,3
-
tCK
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Parameter Minimum time clocks remains ON after CKE asynchronously drops low Output impedance test driver delay MRS command to ODT update delay ODT turn-on delay ODT turn-on ODT turn-on (Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to Power-Down entry latency ODT Power-Down exit latency Symbol -2.5 Min. tIS + tCK (avg)+tIH 0 0 2 tAC(min.) tAC(min.) + 2000 2.5 tAC(min.) tAC(min.) + 2000 3 8 Max. 12 12 2 tAC(max.) + 700 2 x tCK +tAC(max.) + 1000 2.5 tAC(max.) + 600 2.5 x tCK +tAC(max.) + 1000 3 8 Min. tIS + tCK (avg)+tIH 0 0 2 tAC(min.) tAC(min.) + 2000 2.5 tAC(min.) -3
M14D2561616A
Max. 12 12 2 tAC(max.) + 700 2 x tCK +tAC(max.) + 1000 2.5
Unit
Note
tDELAY tOIT tMOD tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ns ns ns tCK ps ps tCK ps ps tCK tCK 15,17 ,18 14,16
tAC(max.) + 600 2.5 x tCK tAC(min.) + 2000 +tAC(max.) + 1000 3 8 3 8
Note: 1. For each of the terms above, if not already an integer, round to the next higher integer. 2. AL: Additive Latency. 3. MRS A12 bit defines which Active Power-Down Exit timing to be applied. 4. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a rising signal and VIL (AC) for a falling signal applied to the device under test. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a rising signal and VIH (DC) for a falling signal applied to the device under test.
6.
tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = Min ( tCH (abs), tCL (abs) ), where: tCH (abs) is the minimum of the actual instantaneous clock HIGH time; tCL (abs) is the minimum of the actual instantaneous clock LOW time;
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7.
M14D2561616A
tQHS accounts for: a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers. tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: a. If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. b. If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. RU stands for round up. WR refers to the tWR parameter stored in the MRS.
8.
9.
10. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tERR (6-10per) of the input clock. (output de-ratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR (6-10per)(min.) = - 272 ps and tERR (6-10per)(max.) = + 293 ps, then tDQSCK (min.)(derated) = tDQSCK (min.) - tERR (6-10per)(max.) = - 400 ps - 293 ps = - 693 ps and tDQSCK (max.) (derated) = tDQSCK (max.) - tERR (6-10per)(min.) = 400 ps + 272 ps = + 672 ps. Similarly, tLZ (DQ) for DDR2-667 de-rates to tLZ (DQ)(min.)(derated) = - 900 ps - 293 ps = - 1193 ps and tLZ (DQ)(max.)(derated) = 450 ps + 272 ps = + 722 ps. 11. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tJIT (per) of the input clock. (output de-ratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT (per)(min.) = - 72 ps and tJIT (per)(max.) = + 93 ps, then tRPRE (min.)(derated) = tRPRE (min.) + tJIT (per)(min.) = 0.9 x tCK (avg) - 72 ps = + 2178 ps and tRPRE (max.)(derated) = tRPRE (max.) + tJIT (per)(max.) = 1.1 x tCK (avg) + 93 ps = + 2843 ps. 12. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tJIT (duty) of the input clock. (output de-ratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT (duty)(min.) = - 72 ps and tJIT (duty)(max.) = + 93 ps, then tRPST (min.)(derated) = tRPST (min.) + tJIT (duty)(min.) = 0.4 x tCK (avg) - 72 ps = + 928 ps and tRPST (max.)(derated) = tRPST (max.) + tJIT (duty)(max.) = 0.6 x tCK (avg) + 93 ps = + 1592 ps. 13. Refer to the Clock Jitter table. 14. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 15. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 16. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tERR (6-10per) of the input clock. (output de-ratings are relative to the SDRAM input clock.) 17. When the device is operated with input clock jitter, this parameter needs to be derated by { - tJIT (duty)(max.) - tERR (6-10per)(max.) } and { - tJIT (duty)(min.) - tERR (6-10per)(min.) } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR (6-10per)(min.) = - 272 ps, tERR (6- 10per)(max.) = + 293 ps, tJIT (duty)(min.) = - 106 ps and tJIT (duty)(max.) = + 94 ps, then tAOF(min.)(derated) = tAOF(min.) + { - tJIT (duty)(max.) tERR (6-10per)(max.) } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and tAOF(max.)(derated) = tAOF(max.) + { - tJIT (duty)(min.) tERR (6-10per)(min.) } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps. 18. For tAOFD of DDR2-667/800, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH (avg), average input clock HIGH pulse width of 0.5 relative to tCK (avg). tAOF (min.) and tAOF (max.) should each be derated by the same amount as the actual amount of tCH (avg) offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH (avg) of 0.48, the tAOF (min.) should be derated by subtracting 0.02 x tCK (avg) from it, whereas if an input clock has a worst case tCH (avg) of 0.52, the tAOF (max.) should be derated by adding 0.02 x tCK (avg) to it. Therefore, we have; tAOF (min.)(derated) = tAC (min.) - [0.5 - Min(0.5, tCH (avg)(min.))] x tCK (avg) tAOF (max.)(derated) = tAC (max.) + 0.6 + [Max(0.5, tCH (avg)(max.)) - 0.5] x tCK (avg) or tAOF (min.)(derated) = Min(tAC (min.), tAC (min.) - [0.5 - tCH (avg)(min.)] x tCK (avg)) tAOF (max.)(derated) = 0.6 + Max(tAC (max.), tAC (max.) + [tCH (avg)(max.) - 0.5] x tCK (avg)), where: tCH (avg)(min.) and tCH (avg)(max.) are the minimum and maximum of tCH (avg) actually measured at the DRAM input balls. Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009 Revision : 1.1 14/59
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ODT DC Electrical Characteristics
Parameter Rtt effective impedance value for 75 setting EMRS(1) [A6, A2] = 0, 1 Rtt effective impedance value for 150 setting EMRS(1) [A6, A2) = 1, 0 Rtt effective impedance value for 50 setting EMRS(1) [A6, A2] = 1, 1 Deviation of VM with respect to VDDQ /2 Note: Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) VM Min. 60 120 40 -6 75
M14D2561616A
Typ.
Max. 90 180 60 +6
Unit

%
150 50 -
Measurement Definition for Rtt(eff) : Rtt(eff) is determined by separately applying VIH(AC) and VIL(AC) to test pin, and then measuring current I(VIH(AC)) and I(VIL(AC)) respectively.
Measurement Definition for VM : Measure voltage (VM) at test pin with no load.
OCD Default Characteristics
Parameter Output impedance Pull-up and pull-down mismatch Output slew rate Note: 1. Absolute specifications: the operation range of Voltage and Temperature. 2. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1,420mV; (VOUT - VDDQ)/IOH must be less than 23.4 for values of VOUT between VDDQ and VDDQ - 280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4 for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage. 4. Slew rate measured from VIL (AC) to VIH (AC). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. Min. 12.6 0 1.5 Typ. 18 Max. 23.4 4 5 Unit Note 1 1,2,3 1,4,5

V/ns
Elite Semiconductor Memory Technology Inc.
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Clock Jitter [ DDR2- 800, 667 ]
Parameter Symbol -2.5 Min. 2500 -100 Max. 8000 100 Min. 3000 -125 -3 Max. 8000 125 100 250 200 175 225 250 250 350 450 0.52 0.52 125
M14D2561616A
Unit ps ps ps ps ps ps ps ps ps ps ps tCK (avg) tCK (avg) ps
Note 1 5 5 6 6 7 7 7 7 7 7 2 3 4
Average clock period tCK (avg) Clock period jitter tJIT (per) Clock period jitter during tJIT (per,lck) -80 80 -100 DLL locking period Cycle to cycle period jitter tJIT (cc) 200 Cycle to cycle clock period jitter tJIT (cc, lck) 160 During DLL locking period Cumulative error across 2 cycles tERR (2per) -150 150 -175 Cumulative error across 3 cycles tERR (3per) -175 175 -225 Cumulative error across 4 cycles tERR (4per) -200 200 -250 Cumulative error across 5 cycles tERR (5per) -200 200 -250 Cumulative error across tERR (6-10per) -300 300 -350 n=6,7,8,9,10 cycles Cumulative error across tERR (11-50per) -450 450 -450 n=11,12,....49,50 cycles Average high pulse width tCH (avg) 0.48 0.52 0.48 Average low pulse width tCL (avg) 0.48 0.52 0.48 Duty cycle jitter tJIT (duty) -100 100 -125 Note: 1. tCK (avg) is calculated as the average clock period across any consecutive 200 cycle window.
2.
tCH (avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
3.
tCL (avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
4.
tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg). tJIT (duty) is not subject to production test. tJIT (duty) = Min./Max. of { tJIT (CH), tJIT (CL)}, where: tJIT (CH) = { tCH j - tCH (avg) where j =1 to 200} tJIT (CL) = {tCL j - tCL (avg) where j =1 to 200} tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg). tJIT (per) = Min./Max. of { tCK j - tCK (avg) where j =1 to 200} tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not subject to production testing.
5.
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6.
M14D2561616A
tJIT (cc) is defined as the difference in clock period between two consecutive clock cycles : tJIT (cc) = Max. of | tCK i +1 - tCK i| tJIT (cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT (cc, lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not subject to production testing. tERR (nper) is defined as the cumulative error across multiple consecutive cycles from tCK (avg). tERR (nper) is not subject to production testing.
7.
8.
These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min. and max. of SPEC values are to be used for calculations in the table below.) Parameter Absolute clock period Absolute clock high pulse width Symbol tCK (abs) Min. Max. tCK (avg)(max.) + tJIT (per)(max.) tCH (avg)(max.) x tCK (avg)(max.) + tJIT (duty)(max.) tCL (avg)(max.) x tCK (avg)(max.) + tJIT (duty)(max.) Unit ps ps ps
tCK (avg)(min.) + tJIT (per)(min.) tCH (avg)(min.) x tCK (avg)(min.) + tCH (abs) tJIT (duty)(min.) tCL (avg)(min.) x tCK (avg)(min.) + Absolute clock low pulse width tCL (abs) tJIT (duty)(min.) Example: For DDR2-667, tCH (abs)(min.) = (0.48 x 3000ps) - 125 ps = 1315 ps
Input Slew Rate De-rating
For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data sheet tIS (base), tDS (base) and tIH (base), tDH (base) value to the tIS, tDS and tIH, tDH de-rating value respectively. Example: tDS (total setup time) = tDS (base) + tDS. Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIH (AC)(min.). Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIL (AC)(max.). If the actual signal is always earlier than the nominal slew rate line between shaded `VREF (DC) to AC region', use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal). If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF (DC) to AC region', the slew rate of a tangent line to the actual signal from the AC level to DC level is used for de-rating value (see the figure of Slew Rate Definition Tangent). Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC)(max.) and the first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC)(min.) and the first crossing of VREF (DC). If the actual signal is always later than the nominal slew rate line between shaded `DC level to VREF (DC) region', use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal). If the actual signal is earlier than the nominal slew rate line anywhere between shaded `DC to VREF (DC) region', the slew rate of a tangent line to the actual signal from the DC level to VREF (DC) level is used for de-rating value (see the figure of Slew Rate Definition Tangent). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH / VIL (AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH / VIL (AC). For slew rates in between the values listed in the tables below, the de-rating values may be obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.
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DQS, 4.0 V/ns
2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 +100 +67 0 +45 +21 0 -
M14D2561616A
De-rating Value of tDS/tDH with Differential DQS(DDR2-667, 800)
differential slew rate 3.0 V/ns 2.0 V/ns
+100 +67 0 -5 +45 +21 0 -14 +100 +67 0 -5 -13 +45 +21 0 -14 -31 -
1.8 V/ns
+79 +12 +7 -1 -10 +33 +12 -2 -19 -42 -
1.6 V/ns
+24 +19 +11 +2 -10 +24 +10 -7 -30 -59 -
1.4 V/ns
+31 +23 +14 +2 -24 +22 +5 -18 -47 -89 -
1.2 V/ns
+35 +26 +14 -12 -52 +17 -6 -35 -77 -140
1.0 V/ns
+38 +26 0 -40 +6 -23 -65 -128
0.8 V/ns
+38 +12 -28 -11 -53 -116
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
Unit ps ps ps ps ps ps ps ps ps
DQ slew rate (V/ns)
De-rating Value of tIS/tIH (DDR2-667, 800)
CLK, CLK differential slew rate 2.0 V/ns 1.5 V/ns
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 tIS +150 +143 +133 +120 +100 +67 0 -5 -13 -22 -34 -60 -100 -168 -200 -325 -517 -1000 tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 tIS +180 +173 +163 +150 +130 +97 +30 +25 +17 +8 -4 -30 -70 -138 -170 -295 -487 -970 tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095
1.0 V/ns
tIS +210 +203 +193 +180 +160 +127 +60 +55 +47 +38 +26 0 -40 -108 -140 -265 -457 -940 tIH +154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065
Unit ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Command / Address slew rate (V/ns)
Elite Semiconductor Memory Technology Inc.
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Slew Rate Definition Nominal
M14D2561616A
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Slew Rate Definition Tangent
M14D2561616A
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Command Truth Table
COMMAND Register Extended MRS Mode Register Set Auto Refresh Refresh Self Refresh Entry Exit
Note 7 Note 7
M14D2561616A
CKE(n-1) CKE(n) H H H L H H H H L H H H
CS L L L L H L L
RAS L L L H X L H
CAS L L L H X H L
WE
DM X X X X X X
BA0,1
A10/AP
A12~A11, A9~A0
Note 1,2
L L H H X H H
BA0=0; OP CODE BA1=1; OP CODE X X V V Row Address L Column Address (A8~A0) Column Address (A8~A0) X
10,12 6,9, 12
Bank Active Auto Precharge Disable Read Auto Precharge Enable Auto Precharge Disable Write Auto Precharge Enable Bank Selection All Banks Entry Active Power-Down Exit Entry Precharge Power-Down Exit DM Device Deselect No Operation
H
H L
1,3
H
H
L
H
L
L
X
V V X
H L H
1,3
Precharge
H H L H L H H H
H L H L H H X X
L H L H L H L H L H L
L X H X H X H X H X X H
H X H X H X H X H X H
L X H X H X H X H X H
X X
X X X X X V X X X X X
4,11, 12,15 4,8, 12,15 4,11, 12,15 4,8, 12,15 16
(OP code = Operand Code, V = Valid, X = Don't Care, H = Logic High, L = Logic Low) Note: 1. BA during a MRS/EMRS command selects which mode register is programmed. 2. MRS/EMRS can be issued only at all bank Precharge state. 3. Burst Reads or Writes at BL = 4 cannot be terminated or interrupted. 4. The Power-Down mode does not perform any Refresh operations. The duration of Power-Down is limited by the Refresh requirements. Need one clock delay to entry and exit mode. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 6. Self Refresh Exit is asynchronous. 7. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock edge. 8. All states not shown are illegal or reserved unless explicitly described elsewhere in this document. 9. On Self Refresh, Exit Deselect or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD is satisfied. 10. Self Refresh mode can only be entered from all banks Idle state. 11. Power-Down and Self Refresh can not be entered while Read or Write operations, MRS/EMRS operations or Precharge operations are in progress. 12. Minimum CKE HIGH / LOW time is tCKE (min). 13. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 14. CKE must be maintained HIGH while the device is in OCD calibration mode. 15. ODT must be driven HIGH or LOW in Power-Down if the ODT function is enabled. 16. Used to mask write data, provided coincident with the corresponding data. Elite Semiconductor Memory Technology Inc.
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Power On and Initialization
M14D2561616A
DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation.
Power-Up and Initialization Sequence
The following sequence is required for Power-Up and Initialization. 1. Apply power and attempt to maintain CKE below 0.2 x VDDQ and ODT (*1) at a low state (all other inputs may be undefined). - VDD(*2), VDDL(*2) and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95V max, AND - VREF tracks VDDQ /2. or - Apply VDD(*2) before or at the same time as VDDL. - Apply VDDL(*2) before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT and VREF. at least one of these two sets of conditions must be met. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Start clock and maintain stable condition. For the minimum of 200us after stable power and clock (CLK, CLK ), then apply NOP or Deselect and take CKE High. Waiting minimum of 400ns then issue Precharge commands for all banks of the device. NOP or Deselect applied during 400ns period. Issue EMRS(2) command. (To issue EMRS(2) command, provide "LOW" to BA0, "HIGH" to BA1.) Issue EMRS(3) command. (To issue EMRS(3) command, provide "HIGH" to BA0 and BA1.) Issue EMRS(1) to enable DLL. (To issue "DLL Enable" command, provide "LOW" to A0, "HIGH" to BA0 and "LOW" to BA1.) Issue a Mode Register Set command for "DLL reset" (*3). (To issue DLL reset command, provide "HIGH" to A8 and "LOW" to BA0-1) Issue Precharge commands for all banks of the device. Issue 2 or more Auto Refresh commands. Issue a Mode Register Set command with LOW to A8 to initialize device operation. (To program operation parameters without resetting the DLL.) At least 200 clocks after step 8, execute OCD calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS(1) OCD default command (A9=A8= A7=1) followed by EMRS(1) OCD calibration mode exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS(1). The DDR2 SDRAM is now ready for normal operation.
13.
Note : *1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. *2) If DC voltage level of VDDL or VDD is intentionally changed during normal operation, (for example, for the purpose of VDD corner test, or power saving) "DLL Reset" must be executed. *3) Every "DLL enable" command resets DLL. Therefore sequence 8 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
Initialization Sequence after Power-UP
tCH tCL
CLK CLK
tIS
CKE
Command
NOP 400ns
PA L L
EMR S(2)
EMRS(3)
E MRS (1 )
MR S
PA L L
REF
REF
MRS
EMRS(1)
EMRS(1)
Any Co mma nd
tRP
tMRD
tMRD
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
Follow OCD Flow C hart
tOIT
Precharge All
DLL enable
DLL R eset
200 Cycle (min.)
O CD default
OCD Calibration mode exit
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Mode Register Definition Mode Register Set [MRS]
M14D2561616A
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency, burst length, burst type, test mode, DLL reset, WR and various vendor specific options to make the device useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after Power-Up for proper operation. The mode register is written by asserting LOW on CS , RAS , CAS , WE , BA0 and BA1 (The device should be in all bank Precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE , BA0 and BA1 going LOW are written in the mode register. The tMRD time is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length is defined by A0 ~ A2. Burst address sequence type is defined by A3, CAS latency (read latency from column address) is defined by A4 ~ A6. The DDR2 doesn't support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recovery time WR is defined by A9 ~ A11. Refer to the table for specific codes.
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
PD
WR
DLL
TM
CAS Latency
BT
Burst Length
Mode Register
Active Power down exit timing A12 0 1 BA1 BA0 0 0 1 1 0 1 0 1 PD Fast Exit (normal) Slow Exit (low power) Mode Register MRS EMRS(1) EMRS(2) EMRS(3) : Reserve Write recovery for Auto Precharge A11 A10 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 WR(cycles) Reserve 2 3 4 5 6 Reserve Reserve A8 0 1
A7 0 1
Mode No Yes
A3 0 1
Burst Type Sequential Interleave
DLL reset No Yes
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Length Reserve Reserve 4 8 Reserve Reserve Reserve Reserve
CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserve Reserve Reserve 3 4 5 6 Reserve
Note: 1. "Reserve" are reserved for future use and must be set to 0. 2. WR(min.) (write recovery for Auto Precharge) is determined by tCK (max.) and WR(max.) is determined by tCK (min.) WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer ( WR[cycles] = tWR (ns)/ tCK (ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
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Burst Address Ordering for Burst Length
Burst Length 4 Starting Column Address (A2, A1,A0) 000 001 010 011 000 001 010 011 100 101 110 111 Sequential Mode 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2
M14D2561616A
Interleave Mode 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
8
Mode Register Set
0 CLK CLK
*1
1
2
3
4
5
6
7
8
CO MMA ND
Precharge All Banks
Mode Register Set
Any Command
tC K
t R P* 2
tMRD
*1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command.
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having the DLL disabled for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_18. The device also supports a weak drive strength option, intended for lighter load and/or point-to-point environments.
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Extended Mode Register Set-1 [EMRS(1)]
M14D2561616A
The EMRS(1) stores the data for enabling or disabling DLL, output driver strength, additive latency, ODT, disable , OCD program. The default value of the EMRS(1) is not defined, therefore EMRS(1) must be written after power up for proper operation. The EMRS(1) is written by asserting LOW on CS , RAS , CAS , WE , BA1 and HIGH on BA0 (The device should be in all bank Precharge with CKE already high prior to writing into EMRS(1)). The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA1 going LOW and BA0 going HIGH are written in the EMRS(1). The tMRD time is required to complete the write operation to the EMRS(1). The EMRS(1) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. A1 is used for reducing output driver strength. The additive latency is defined by A3~A5. A7~A9 are used for OCD control. A10 is used for disable. ODT setting is defined by A2 and A6.
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
Qoff
0
OCD program
Rtt
Additive Latency
Rtt
ODS
DLL
A0 A6 0 0 1 1 A2 0 1 0 1 Rtt (nominal) Disable 75 150 50 0 1
DLL Enable Enable Disable
A10 0 1
Enable Enable Disable
A1 0 1 Additive Latency A5 0 0 0 0 1 1 1 1 A4 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1
Output Driver Strength Control Normal (100%) Weak (60%)
A12 0 1
Qoff Output buffer enable Output buffer disable
Latency 0 1 2 3 4 Reverse Reverse Reverse
Driver Impedance Adjustment BA1 BA0 0 0 1 1 0 1 0 1 Mode Register MRS EMRS(1) EMRS(2) EMRS(3): Reserve A9 0 0 0 1 1 A8 0 0 1 0 1 A7 0 1 0 0 1 OCD operation OCD calibration mode exit Drive-1 Drive-0 Adjustable mode OCD default state
Note: 1. 2. 3. 4.
A11 and "Reserve" are reserved for future use and must be set to 0. When adjustable mode of driver impedance is issued, the previously set value of AL must be applied. After setting to default state of driver impedance, OCD calibration mode needs to be exited by setting A9~A7 to 000. Qoff: the feature is intended to be used during IDD characterization of read current. When disabled, all outputs (DQs, DQS and ) are disabled.
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ESMT
Extended Mode Register Set-2 [EMRS(2)]
M14D2561616A
The EMRS(2) stores the data for enabling or disabling high temperature self refresh rate. The default value of the EMRS(2) is not defined, therefore EMRS(2) must be written after power up for proper operation. The EMRS(2) is written by asserting LOW on CS , RAS , CAS , WE , BA0 and HIGH on BA1 (The device should be in all bank Precharge with CKE already high prior to writing into EMRS(2)). The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0 going LOW and BA1 going HIGH are written in the EMRS(2). The tMRD time is required to complete the write operation to the EMRS(2). The EMRS(2) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the idle state. A7 is used for high temperature self refresh rate enable or disable.
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
0
SRF
0
BA1 BA0 0 0 1 1 0 1 0 1
Mode Register MRS EMRS(1) EMRS(2) EMRS(3): Reserve
A7 0 1
High Temperature Self Refresh rate Disable Enable
Note: All bits except A7, BA0 and BA1 are reserved for future use and must be set to 0.
Extended Mode Register Set-3 [EMRS(3)]
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
1
0
BA1 BA0 0 0 1 1 0 1 0 1
Mode Register MRS EMRS(1) EMRS(2) EMRS(3): Reserve
Note: EMRS(3) is reserved for future. All bits except BA0 and BA1 are reserved for future use and must be set to 0 when setting to mode register during initialization. Elite Semiconductor Memory Technology Inc.
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ESMT
Off-Chip Driver (O CD) Impedance Adjustment
M14D2561616A
DDR2 SDRAM supports driver calibration feature. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment.
OCD Flow Chart
MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS(1) : OCD calibration mode exit
EMRS(1) : Driver-1 DQ & DQS High ; DQS Low
EMRS(1) : Driver-0 DQ & DQS Low ; DQS High
Test
ALL OK
ALL OK
Test Need Calibration EMRS(1) : OCD calibration mode exit
Need Calibration EMRS(1) : OCD calibration mode exit
EMRS(1) : Enter Adjustable mode
EMRS(1) : Enter Adjustable mode
BL=4 code input to all DQs Inc, Dec, or NOP
BL=4 code input to all DQs Inc, Dec, or NOP
EMRS(1) : OCD calibration mode exit
EMRS(1) : OCD calibration mode exit
EMRS(1) : OCD calibration mode exit
End
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ESMT
EMRS(1) for OCD Impedance Adjustment
M14D2561616A
OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode, all outputs are driven out by DDR2 SDRAM. In Drive-1mode, all DQ, DQS signals are driven HIGH and all signals are driven LOW. In Drive-0 mode, all DQ, DQS signals are driven LOW and all signals are driven HIGH. In adjustable mode, BL = 4 of operation code data must be used. In case of OCD default state, output driver characteristics have a nominal impedance value of 18 during nominal temperature and voltage conditions. Output driver characteristics for OCD default state are specified in OCD default characteristics table. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if weak strength is set or adjustable mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A9-A7 as '000' in order to maintain the default or calibrated value.
Driver Impedance Adjustment Mode
A9 0 0 0 1 1 A8 0 0 1 0 1 A7 0 1 0 0 1 Operation OCD calibration mode exit Device-1: DQ,DQS High and Device-0: DQ,DQS Low and Adjustable mode OCD default state
Low High
Adjust OCD Impedance
To adjust output driver impedance, controllers must issue EMRS(1) command for adjustable mode along with a 4bit burst code to DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in the following table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DQs simultaneously and after OCD calibration, all DQs of a given device will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the 16 step range. When Adjustable mode command is issued, AL from previously set value must be applied.
OCD Adjustment Table
DT0 0 0 0 0 1 0 0 1 1 DT1 DT2 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 0 0 1 Others DT3 0 1 0 0 0 1 0 1 0 Pull-up driver strength NOP Increase by 1 step Decrease by 1 step NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Decrease by 1 step Reserve Pull-down driver strength NOP NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step Reserve
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OCD Adjustable Mode
M14D2561616A
CLK CLK
Command
EMRS(1)
NOP WL tWR
EMRS(1)
NOP
DQS, DQS tDS tDH DQ DT0 DT1 DT2 DT3
DM
OCD adjustable
OCD calibration mode exit
Note: For proper operation of adjustable mode, WL = RL - 1 = AL + CL - 1 clocks and tDS / tDH should be met as the above timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by MRS addressing mode (ie. sequential or interleave).
OCD Driver Mode
CLK CLK
Command
EMRS(1)
NOP
EMRS(1)
DQS, DQS
High-Z
DQs high and DQS low for Drive-1, DQs low and DQS high for Drive-0
High-Z
DQs high for Drive-1
DQ
tOIT
DQs low for Drive-0
tOIT
Enter drive mode
OCD Calibration mode exit
Note: Drive mode, both Drive-1 and Drive-0, is used for controllers to measure DDR2 SDRAM driver impedance. In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the above timing diagram.
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ESMT
ODT (On Die Termination)
M14D2561616A
On Die Termination (ODT) is a feature that allows a DDR2 SDRAM to turn on/off termination resistance for each DQ, all DQS/ , and all DM signals via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all devices. The ODT function is supported for Active and Standby modes. ODT is turned off and not supported in Self Refresh mode.
Timing for ODT Update Delay
CLK CLK
Command tAOFD ODT
EMRS(1)
NOP tIS
tMOD(max.) tMOD(min.) Internal Rtt Setting Old setting Updating New Setting
Note: tAOFD must be met before issuing EMRS(1) command. ODT must remain low for the entire duration of tMOD window.
ODT Timing for Active and Standby Mode
T0 CLK CLK T1 T2 T3 T4 T5 T6
CKE tIS ODT tAOND Internal Term Res. Rtt tAON(min.) tAON(max.) tAOF(min.) tAOFD tIS
tAOF(max.)
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ODT Timing for Power-Down Mode
T0 CLK CLK T1 T2 T3 T4 T5
M14D2561616A
T6
CKE tIS ODT tAOFPD(max.) Internal Term Res. tAONPD(min.) tAONPD(max.) tAOFPD(min.) Rtt tIS
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ODT Timing Mode Switch at Entering Power-Down Mode
T-5
CLK CLK
M14D2561616A
T-4
T-3
T-2
T-1
T0
T1
T2
T3
tANPD
CKE
tIS
Entering slow exit Active Power-Down mode or Precharge Power-Down mode.
tIS
ODT
tAOFD
Internal Term Res.
Rtt tIS
Active and Standby mode timings to be applied.
ODT
tAOFPD(max.)
Internal Term Res.
Rtt tIS
Power-Down mode timings to be applied.
ODT
tAOND
Internal Term Res.
Rtt tIS
Active and Standby mode timings to be applied.
ODT
tAONPD(max.)
Internal Term Res.
Rtt
Power-Down mode timings to be applied.
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ODT Timing Mode Switch at Exiting Power-Down Mode
T0
CLK CLK
M14D2561616A
T1
T4
T5
T6
T7
T8
T9
T10
T11
CKE
tIS
tAXPD
Exiting from slow Active Power-Down mode or Precharge Power-Down mode.
tIS
ODT Active and Standby mode timings to be applied.
tAOFD
Internal Term Res.
Rtt
tIS
ODT Power-Down mode timings to be applied.
tAOFPD(max.)
Internal Term Res.
Rtt tIS
ODT Active and Standby mode timings to be applied.
tAOND
Internal Term Res.
Rtt tIS
ODT Power-Down mode timings to be applied.
tAONPD(max.)
Internal Term Res.
Rtt
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Precharge
M14D2561616A
The Precharge command is used to precharge or close a bank that has activated. The command is issued when CS , RAS and
WE are LOW and CAS is HIGH at the rising edge of the clock. The Precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) and A10 are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the Precharge command can be issued. After tRP from the precharge, a Bank Active command to the same bank can be initiated.
Bank Selection for Precharge by Address bits A10/AP 0 0 0 0 1 BA1 0 1 0 1 X BA0 0 0 1 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode, DDR2 SDRAM would ignore all the control inputs. The DDR2 SDRAM are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and NOP, the device should finish the current operation when this command is issued.
Bank Active
The Bank Active command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the clock (CLK). The DDR2 SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Active command to the first Read or Write command must meet or exceed the minimum of RAS to CAS delay time (tRCD(min.)). Once a bank has been activated, it must be precharged before another Bank Active command can be applied to the same bank. The minimum time interval between interleaved Bank Active command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min).
Bank Active Command Cycle
T0
CLK CLK
Posted READ
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
Command
ACT
Bank A Row Addr.
ACT
Bank B Row Addr.
Posted READ
PRE Bank A
PRE Bank B
ACT
Bank A Row Addr.
Address
Bank A Col. Addr.
Bank B Col. Addr.
tCCD tRCD=1 tRRD
Additive latency (AL)
Bank A Read begins tRP tRC Bank A Precharge Bank B Precharge Bank A Active
tRAS Bank A Active Bank B Active
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Read Bank
M14D2561616A
This command is used after the Bank Active command to initiate the burst read of data. The Read command is initiated by activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the Bank Active command to initiate the burst write of data. The Write command is initiated by activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command.
Posted
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the Bank Active command (or any time during the tRRD period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCD(min), then AL (greater than 0) must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow seamless bursts.
Read followed by a Write to the Same Bank
< AL= 2; CL= 3 ; BL = 4>
-1 CLK CLK
Active Bank A Read Bank A Write Bank A
0
1
2
3
4
5
6
7
8
9
10
11
12
CMD
AL = 2 DQS/DQS
CL = 3
WL = RL -1 =4
>= tRCD
RL = AL + CL = 5
Dout0 Dout1 Dout2 Dout3
DQ
Din0 Din1 Din2 Din3
< AL= 0; CL= 3; BL = 4 >
-1 CLK CLK AL = 0 CMD
Active Bank A Read Bank A Write Bank A
0
1
2
3
4
5
6
7
8
9
10
11
12
CL = 3
WL = RL -1 = 2
DQS/DQS
>= tRCD
RL = AL + CL = 3
Dout0 Dout1 Dout2 Dout3
DQ
Din0 Din1 Din2 Din3
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Essential Functionality for DDR2 SDRAM Burst Read Operation
M14D2561616A
The Burst Read command is initiated by having CS and CAS LOW while holding RAS and WE HIGH at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The DQS is driven LOW 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of DQS. Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the MRS and the AL is defined by the EMRS(1).
Read (Data Output) Timing
tCH CLK CLK DQS DQS tRPRE DQ tDQSQ(max.) tQH
Dout0 Dout1 Dout2
tCL
tRPST
Dout3
tDQSQ(max.) tQH
Burst Read
< RL= 5 (AL= 2; CL= 3); BL= 4 >
T0
CLK CLK CMD
Posted CAS READ A
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP =< tDQSCK
NOP
NOP
NOP
DQS,DQS
AL = 2
DQs
CL = 3 RL = 5
DoutA0 DoutA1 DoutA2 DoutA3
< RL= 3 (AL= 0; CL= 3); BL= 8 >
T0
CLK CLK CMD
T1
T2
T3
T4
T5
T6
T7
T8
READ A
NOP
NOP
NOP =< tDQSCK
NOP
NOP
NOP
NOP
NOP
DQS,DQS
CL = 3 RL = 3
DQs DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
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Burst Read followed by Burst Write
< RL= 5; WL= (RL-1) = 4; BL= 4 >
T0
CLK CLK CMD
Posted CAS READ A Posted CAS NOP NOP WRITE A tRTW (Read to Write-turn around-time)
M14D2561616A
T1
Tn-1
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
NOP
NOP
NOP
NOP
NOP
DQS,DQS
RL = 5 WL = RL-1 = 4
DQs DoutA0 DoutA1 DoutA2 DoutA3 DinA0 DinA1 DinA2 DinA3
Note: The minimum time from the Burst Read command to the Burst Write command is defined by a read to write-turn around-time(tRTW), which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
Seamless Burst Read
< RL= 5; AL= 2; CL= 3; BL = 4 >
T0
CLK CLK CMD
Posted CAS READ A
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Posted CAS READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
AL = 2
DQs
CL = 3 RL = 5
DoutA0 DoutA1 DoutA2 DoutA3 DoutB0 DoutB1 DoutB2
Note: The seamless burst read operation is supported by enabling a Read command at every other clock for BL = 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
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Burst Write Operation
M14D2561616A
The Burst Write command is issued by having CS , CAS and WE LOW while holding RAS HIGH at the rising edge of the clock (CLK). The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1); and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR).
Write (Data Input) Timing
tDQSH DQS DQS DQS DQS tWPRE DQ Din0 tDS DM Din1 tDS Din2 tDH Din3 tDH tWPST tDQSL
Burst Write
< RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 >
T0
CLK CLK CMD
Posted CAS WRITE A
T1
T2
T3
T4
T5
T6
T7
Tn
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
Case1 : with tDQSS(max)
DQS,DQS
WL = RL -1 = 4
DQs
tDQSS
DinA0
tDSH
DinA1 DinA2 DinA3
>= tWR
Case2 : with tDQSS(min)
DQS,DQS
tDQSS WL = RL -1 = 4
tDSS >= tWR
DQs
DinA0
DinA1 DinA2 DinA3
< RL= 3 (AL= 0; CL= 3); WL= 2; BL= 4 >
T0
CLK CLK CMD
T1
T2
T3
T4
T5
T6
T7
Tn
WRITE A
NOP
NOP tDQSS
NOP
NOP
NOP
Precharge
NOP
Bank A Active
DQS,DQS
WL = RL -1 = 2
DQs DinA0 DinA1 DinA2 DinA3
tWR
>= tRP
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Burst Write followed by Burst Read
< RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 >
T0
CLK CLK CMD
M14D2561616A
T1
T2
T3
T4
T5
T6
T7
T8
T9
Write to Read = CL -1+BL/2+tWTR NOP NOP
DQS
NOP
NOP
Posted CAS READ A
NOP
NOP
NOP
NOP
NOP
DQS,DQS
DQS
WL = RL -1 = 4
AL = 2 RL = 5 > = tWTR
CL = 3
DQ
DinA0
DinA1 DinA2 DinA3
DoutA0
Note: The minimum number of clock from the Burst Write command to the Burst Read command is [CL - 1 + BL/2 + tWTR]. This tWTR is not a write recovery time (WR) but the time required to transfer the 4 bit write data from the input buffer into sense amplifiers in the array.
Seamless Burst Write
< RL= 5; WL= 4; BL= 4 >
T0
CLK CLK CMD
Posted CAS WRITE A
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Posted CAS WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
WL = RL-1 = 4
DQs
DinA0 DinA1 DinA2 DinA3 DinB0 DinB1 DinB2 DinB3
Note: The seamless burst write operation is supported by enabling a Write command at every other clock for BL = 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
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Read Interrupted by a Read
M14D2561616A
Burst Read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not allowed.
< CL= 3; AL= 0; RL= 3; BL= 8 >
CLK CLK CMD
READ A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
DQs
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Note: 1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited. 3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt timings are prohibited. 4. Read burst interruption is allowed to any bank inside DRAM. 5. Read burst with Auto Precharge enabled is not allowed to interrupt. 6. Read burst interruption is allowed by another Read with Auto Precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the MRS and not the actual burst (which is shorter because of interrupt).
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Write Interrupted by a Write
M14D2561616A
Burst Wirte can only be interrupted by another Write with 4 bit burst boundary. Any other case of Write interrupt is not allowed.
< CL= 3; AL= 0; RL= 3; WL= 2; BL= 8 >
T0
CLK CLK CMD
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Write A
NOP
Write B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
DQs
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Note: 1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or Precharge command is prohibited. 3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt timings are prohibited. 4. Write burst interruption is allowed to any bank inside DRAM. 5. Write burst with Auto Precharge enabled is not allowed to interrupt. 6. Write burst interruption is allowed by another Write with Auto Precharge command. 7. All command timings are referenced to burst length set in the MRS. They are not referenced to actual burst. For example, minimum Write to Precharge timing is WL+BL/2+ tWR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009 Revision : 1.1 41/59
ESMT
Burst Read Followed by Precharge
M14D2561616A
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(tRTP, 2) - 2 clocks. For the earliest possible Precharge, the Precharge command may be issued on the rising edge which is "Additive latency (AL) + BL/2 clocks" after a Read command. A new Bank Active command may be issued to the same bank after the Precharge time (tRP). A Precharge command cannot be issued until tRAS is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4, this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8, this is the time from AL + 2 clocks after the Read to the Precharge command. < RL= 4 (AL= 1; CL= 3) >
T0
CLK CLK CMD
Posted CAS READ A
T1
T2
T3
T4
T5
T6
T7
T8
NOP NOP AL + BL/2 clks
Precharge
NOP
NOP
NOP
Bank A Active
NOP
BL = 4
DQS,DQS
AL = 1
DQs
CL = 3 RL = 4 >= tRAS >= tRTP
>= tRP
DoutA0 DoutA1 DoutA2 DoutA3
CL = 3 NOP NOP
Precharge A
CMD
Posted CAS READ A
NOP NOP AL + BL/2 clks
NOP
NOP
NOP
BL = 8
DQS,DQS
AL = 1
DQs
CL = 3 RL = 4
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
>= tRTP
< RL= 5 (AL= 2; CL= 3); BL= 4 >
T0
CLK CLK CMD
Posted CAS READ A
T1
T2
T3
T4
T5
T6
T7
T8
NOP NOP AL + BL/2 clks
NOP
Precharge A
NOP >= tRP
NOP
Bank A Active
NOP
DQS,DQS
DQs
AL = 2 RL = 5 >= tRAS >= tRTP
CL = 3
DoutA0 DoutA1 DoutA2 DoutA3
CL = 3
< RL= 6 (AL= 2; CL= 4); BL= 4 >
T0
CLK CLK CMD
Posted CAS READ A
T1
T2
T3
T4
T5
T6
T7
T8
NOP NOP AL + BL/2 clks
NOP
Precharge A
NOP >= tRP
NOP
Bank A Active
NOP
DQS,DQS
AL = 2
DQs
CL = 4 RL = 6 >= tRAS >= tRTP CL = 4
DoutA0 DoutA1 DoutA2 DoutA3
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ESMT
< RL= 4 (AL= 0; CL= 4); BL=8 >
T0
CLK CLK CMD
Posted CAS WRITE A
M14D2561616A
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
Precharg A
NOP > = tRP
NOP
Bank A Active
AL+2 clks + max(tRTP;2)
DQS,DQS
AL = 0
DQs
CL = 4 RL = 4
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
>= tRAS
Burst Write Followed by Precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 clocks + tWR. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the Burst Write to the Precharge command. No Precharge command should be issued prior to the tWR delay.
< WL= (RL-1) = 3; BL=4>
T0
CLK CLK CMD
Posted CAS WRITE A
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP > = tWR
NOP
Precharg A
DQS,DQS
WL = 3
DQs DinA0 DinA1 DinA2 DinA3
< WL= (RL-1) = 4; BL=4 >
T0
CLK CLK CMD
Posted CAS WRITE A
T1
T2
T3
T4
T5
T6
T7
T9
NOP
NOP
NOP
NOP
NOP
NOP
NOP > = tWR
Precharg A
DQS,DQS
WL = 4
DQs DinA0 DinA1 DinA2 DinA3
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ESMT
Write data mask by DM
M14D2561616A
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAM, Consistent with the implementation on DDR2 SDRAM. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles.
Data Mask Timing
T1
DQS DQS
T2
T3
T4
T5
Tn
DQ
Din
Din
Din
Din
Din
Din
Din
Din
Din
DM
Write mask Iatency = 0
Example: < WL= 3; AL= 0; BL= 4 >
T0
CLK CLK
T1
T2
T3
T4
T5
T6
T7
T8
tWR
Command
WRIT
NOP WL tDQSS
[tDQSS(min.)]
DQS,DQS DQ
Din0
Din2
DM
[tDQSS(max.)]
DQS,DQS DQ
WL
tDQSS
Din0
Din2
DM
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ESMT
Read with Auto Precharge
M14D2561616A
If A10 is HIGH when a Read command is issued, the Read with Auto Precharge function is engaged. The device starts an Auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than the Read with AP command if tRAS (min) and tRTP(min) are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto Precharge operation will be delayed until tRAS(min) is satisfied. If tRTP (min) is not satisfied at the edge, the start point of Auto Precharge operation will be delayed until tRTP (min) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4, the minimum time from Read_AP to the next Bank Active command becomes AL + (tRTP + tRP)*. For BL = 8, the time from Read_AP to the next Bank Active command is AL + 2 + (tRTP + tRP)*. (Note: "*" means "rouded up to the next integer").
< RL= 4 (AL= 1; CL= 3) >
T0
CLK CLK CMD
Posted CAS READ A Autoprecharge
T1
T2
T3
T4
T5
T6
T7
T8
NOP NOP AL+BL/2 clks
NOP
NOP
NOP
NOP > = tRP
NOP
Bank A Active
BL = 8 t RTP <= 2 clocks
DQS,DQS
AL = 1
DQs
CL = 3 RL = 4
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
>= tRTP tRTP Precharge begins here
CMD
Posted CAS READ A Autoprecharge
NOP NOP >=AL+tRTP+tRP
NOP
NOP
NOP
NOP
Bank A Active
NOP
BL = 4 t RTP > 2 clocks
DQS,DQS
AL = 1
DQs
CL = 3 RL = 4
DoutA0 DoutA1 DoutA2 DoutA3
tRTP
tRP Precharge begins here
A new Bank Active command may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The Precharge time (tRP) has been satisfied from the clock at which the Auto Precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
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ESMT
< RL= 5 (AL= 2; CL= 3); BL= 4; tRCD = 3 clocks; tRTP <= 2 clocks >
T0
CLK CLK CMD
Posted CAS READ A Autoprecharge
M14D2561616A
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank A Active
>= tRAS(min)
Autoprecharge begins
tRC Limit
DQS,DQS
AL = 2 RL = 5
DQs
CL = 3
>= tRP
DoutA0 DoutA1 DoutA2 DoutA3
>= tRC
CLK CLK CMD
Posted CAS READ A Autoprecharge
NOP
NOP
NOP
NOP
NOP
NOP
Bank A Active
NOP
>= tRAS(min)
Autoprecharge begins
tRP Limit
DQS,DQS
AL = 2 RL = 5
DQs
CL = 3
>= tRP
DoutA0 DoutA1 DoutA2 DoutA3
>= tRC
Write with Auto Precharge
If A10 is HIGH when a Write command is issued, the Write with Auto Precharge function is engaged. The device automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). The Bank Active command undergoing Auto Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. < WR = 2; BL= 4; tRP = 3 clocks >
T0
CLK CLK CMD
Posted CAS WRITE A Autoprecharge
T1
T2
T3
T4
T5
T6
T7
Tm
NOP
NOP
NOP
NOP
NOP
NOP
Auto Precharge begins
NOP
Bank A Active
tRC Limit
DQS,DQS
WL = RL-1 = 2
DQs
>= tWR
DinA0 DinA1 DinA2 DinA3
>= tRP
>= tRC
CLK CLK CMD
Posted CAS WRITE A Autoprecharge
T0
T3
T4
T5
T6
T7
T8
T9
T12
NOP
NOP
NOP
NOP
NOP
NOP
Auto Precharge begins
NOP
Bank A Active
tWR + tRP
DQS,DQS
WL = RL-1 = 4
DQs DinA0 DinA1 DinA2 DinA3
>= tWR
>= tRP
>= tRC
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ESMT
Auto Refresh & Self Refresh Auto Refresh
M14D2561616A
An Auto Refresh command is issued by having CS , RAS and CAS held LOW with CKE and WE HIGH at the rising edge of the clock(CLK). All banks must be precharged and idle for tRP(min) before the Auto Refresh command is applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Bank Active command or subsequent Auto Refresh command must be greater than or equal to the tRFC(min).To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh commands can be posted, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 9 x tREFI.
CLK CLK
COMMAND
PRE
Au t o Refresh
CMD
CKE = High tRP tRFC
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ESMT
Self Refresh
M14D2561616A
A Self Refresh command is defined by having CS , RAS , CAS and CKE held LOW with WE HIGH at the rising edge of the clock (CLK). ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS(1) command. Once the command is registered, CKE must be held LOW to keep the device in Self Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the device has entered Self Refresh mode, all of the external signals except CKE, are "don't care". For proper Self Refresh operation all power supply pins (VDD, VDDQ, VDDL and VREF) must be at valid levels. The device initiates a minimum of one refresh command internally within tCKE period once it enters Self Refresh mode. The clock is internally disabled during Self Refresh operation to save power. Self Refresh mode must be remained tCKE (min). The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self Refresh operation. The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of tXSRD(min) must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSRD for proper operation except for Self Refresh re-entry. Upon exit from Self Refresh, the device can be put back into Self Refresh mode after waiting tXSNR(min) and issuing one Refresh command. NOP or deselect commands must be registered on each positive clock edge during the Self Refresh exit interval tXSNR. ODT should be turned off during tXSRD. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the device requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode.
T0 tCK tCH tCL
CLK CLK
T1
T2
T3
T4
T5
T6
Tm
Tn
tRP
>= tXSNR >= tXSRD
CKE
tAOFD
tIS
tIS
ODT
tIS tIS
Command
tIH
Note: 1. Device must be in the "All banks idle" state prior to entering Self Refresh mode. 2. ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again when tXSRD timing is satisfied. 3. tXSRD is applied for a Read or a Read with Auto Precharge command. 4. tXSNR is applied for any command except a Read or a Read with Auto Precharge command.
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ESMT
Power-Down
M14D2561616A
Power-Down is synchronously entered when CKE is registered LOW (no accesses can be in progress). CKE is not allowed to go LOW while MRS or EMRS command time, or read or write operation is in progress. CKE is allowed to go LOW while any of other operations such as Bank Active, Precharge or Auto Precharge, or Auto Refresh is in progress. The DLL should be in a locked state when Power-Down is entered. Otherwise DLL should be reset after exiting Power-Down mode for proper read operation. If Power-Down occurs when all banks are idle, this mode is referred to as Precharge Power-Down; if Power-Down occurs when there is a Bank Active command in any bank, this mode is referred to as Active Power-Down. Entering Power-Down deactivates the input and output buffers, excluding CLK, CLK , ODT and CKE. Also the DLL is disabled upon entering Precharge Power-Down or slow exit Active Power-Down, but the DLL is kept enabled during fast exit Active Power-Down. In Power-Down mode, CKE LOW and a stable clock signal must be maintained at the inputs of the device, and ODT should be in a valid state but all other input signals are "Don't Care". CKE LOW must be maintained until tCKE has been satisfied. Power-Down duration is limited by 9 times tREFI of the device. The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). CKE HIGH must be maintained until tCKE has been satisfied. A valid, executable command can be applied with Power-Down exit latency, tXP, tXARD, or tXARDS, after CKE goes HIGH.
CLK CLK
tIS tIH
CKE
tIS tIH
tIH
tIS
tIH
Command
VALID
NOP
NOP
VALID
VALID
VALID
tCKE
tCKE tXP, tXARD, tXARDS tCKE Exit power-down mode : Don't care
Enter power-down mode
Read to Power-Down Entry
T0
CLK CLK
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CKE should be kept high until the end of burst operation
Command
READ High
CKE
BL = 4
DQS DQS
AL + CL
DQ DoutA0 DoutA1 DoutA2 DoutA3
T0
CLK CLK Command
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
READ High
CKE should be kept high until the end of burst operation
CKE
BL = 8
DQS DQS
AL + CL
DQ DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
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ESMT
Read with Auto Precharge to Power-Down Entry
T0
CLK CLK Command
M14D2561616A
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
READ
PRE AL+BL/2 with tRTP =7.5ns and tRAS(min.) satisfied
CKE should be kept high until the end of burst operation
CKE
BL = 4
DQS DQS
AL + CL
DQ DoutA0 DoutA1 DoutA2 DoutA3
T0
CLK CLK
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
Start internal precharge
Command
READ
PRE AL+BL/2 with tRTP = 7.5ns and tRAS(min.) satisfied
CKE should be kept high until the end of burst operation
CKE
BL = 8
DQS DQS
AL + CL
DQ DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
Write to Power-Down Entry
T0
CLK CLK Command
T1
Tm
Tm+1
Tm+2
Tm+3
Tx
Tx+1
Tx+2
Ty
Ty+1
Ty+2
Ty+3
WRITE
CKE
tWTR
BL = 4 DQS DQS
WL
DQ DinA0 DinA1 DinA2 DinA3
T0
CLK CLK
T1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Command
WRITE
CKE
tWTR
BL = 8 DQS DQS
WL
DQ DinA0 DinA1 DinA2 DinA3 DinA4 DinA5 DinA6 DinA7
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ESMT
Write with Auto Precharge to Power-Down Entry
T0
CLK CLK Command
M14D2561616A
T1
Tm
Tm+1
Tm+2
Tm+3
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
WRITE A
PRE
CKE
tWR
BL = 4 DQS DQS
WL
DQ DinA0 DinA1 DinA2 DinA3
T0
CLK CLK
T1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Command
WRITE A
PRE
CKE
tWR
BL = 8 DQS DQS
WL
DQ DinA0 DinA1 DinA2 DinA3 DinA4 DinA5 DinA6 DinA7
Auto Refresh/ Bank Active/ Precharge to Power-Down Entry
T0
CLK CLK Command
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CMD CKE can go to low one clock after a command
CKE
Note: CMD could be Auto Refresh/ Bank Active/ Precharge command.
MRS/EMRS to Power-Down Entry
T0 CLK CLK Command CKE tMRD
MRS/ EMRS
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
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ESMT
Asynchronous CKE Low event
M14D2561616A
DDR2 SDRAM requires CKE to be maintained "HIGH" for all valid operations as defined in this data sheet. If CKE asynchronously drops "LOW" during any valid operation, the device is not guaranteed to preserve the contents of array. If this event occurs, memory controller must satisfy tDELAY before turning off the clocks. Stable clocks must exist at the input of device before CKE is raised "HIGH" again. The device must be fully re-initialized (steps 4 ~ 13) as described in initialization sequence. The device is ready for normal operation after the initialization sequence.
Stable clocks tCK CLK CLK tDELAY
CKE
CKE asynchronously drops low
Clocks can be turned off after this point
Clock Frequency change in Precharge Power-Down mode
DDR2 SDRAM input clock frequency can be changed under following condition: The device is in Precharge Power-Down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. The device input clock frequency is allowed to change only between tCK (min) and tCK (max). During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is changed, stable new clocks must be provided before Precharge Power-Down may be exited and DLL must be RESET via MRS after Precharge Power-Down exit. Depending on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock period, ODT must remain off. After the DLL lock time, the device is ready to operate with new clock frequency.
T0 CLK CLK command CKE
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2
Ty+3
Ty+4
Tz
NOP NOP
NOP
NOP
DLL Reset
NOP
Vaild
ODT
Frequency change occurs here tRP tAOFD Minimum 2 clocks required before changing frequency txP
200 clocks
Stable new clock before power down exit
ODT is off during DLL RESET
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ESMT
Functional Truth Table
Current State CS H L L IDLE L L L L H L L BANK ACTIVE L L L L L H L L READ L L L L L H L L L L L L L RAS X H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L CAS X H L H H L L X H L L H H L L X H L L H H L L X H L L H H L L
WE
M14D2561616A
Address X X BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 /A10 X Op-Code Mode-Add X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add
Command DESEL NOP
Action NOP or Power-Down NOP or Power-Down
X H X H L H L X H H L H L H L X H H L H L H L X H H L H L H L
READ / READA / ILLEGAL (*1) WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS DESEL NOP READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS DESEL NOP READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS DESEL NOP READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS Bank Active, Latch RA Precharge / Precharge All Refresh (*2) Mode Register setting / Extended Mode Register setting (*2) NOP NOP Begin Read, Latch CA, Determine Auto Precharge Begin Write, Latch CA, Determine Auto Precharge ILLEGAL (*1) Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst, Latch CA, Begin New Read, Determine Auto Precharge (*1, 4) ILLEGAL (*1) ILLEGAL (*1) ILLEGAL (*1) / ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL (*1) Terminate Burst, Latch CA, Begin new Write, Determine Auto-Precharge (*1, 4) ILLEGAL (*1) ILLEGAL (*1) / ILLEGAL ILLEGAL ILLEGAL
WRITE
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ESMT
Current State CS H L L READ with AUTO PRECHARGE L L L L L H L L WRITE with AUTO PRECHARGE L L L L L H L L PRE-CHARGIN G L L L L H L L ROW ACTIVATING L L L L RAS X H H H L L L L X H H H L L L L X H H L L L L X H H L L L L CAS X H L L H H L L X H L L H H L L X H L H H L L X H L H H L L
WE
M14D2561616A
Address X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add X X BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add Command DESEL NOP READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS DESEL NOP READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS DESEL NOP Action NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL (*1) ILLEGAL (*1) ILLEGAL (*1) ILLEGAL (*1) / ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL (*1) ILLEGAL (*1) ILLEGAL (*1) ILLEGAL (*1) / ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRP) NOP (Idle after tRP)
X H H L H L H L X H H L H L H L X H X H L H L X H X H L H L
READ / READA / ILLEGAL (*1) WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS DESEL NOP ILLEGAL (*1) NOP (Idle after tRP) ILLEGAL ILLEGAL NOP (Bank Active after tRCD) NOP (Bank Active after tRCD)
READ / READA / ILLEGAL (*1, 5) WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS ILLEGAL (*1) ILLEGAL ILLEGAL ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009 Revision : 1.1 54/59
ESMT
Current State CS H L L WRITE RECOVERING L L L L L H L WRITE RECOVERING with AUTO PRECHARGE L L L L L H L L REFRESH L L L L H L (Extended) MODE REGISTER SETTING L L L L L RAS X H H H L L L L X H H L L L L X H H L L L L X H H L L L L CAS X H L L H H L L X H L H H L L X H L H H L L X H L H H L L
WE
M14D2561616A
Address X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add X X BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add X X BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add X X BA, CA, A10 BA, RA BA, A10 / A10 X Op-Code Mode-Add Command DESEL NOP READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS DESEL NOP Action NOP (Bank Active after tWR) NOP (Bank Active after tWR) ILLEGAL (*1, 6) WRITE / WRITEA ILLEGAL (*1) ILLEGAL (*1) / ILLEGAL ILLEGAL ILLEGAL NOP (Bank Active after tWR) NOP (Bank Active after tWR)
X H H L H L H L X H X H L H L X H X H L H L X H X H L H L
READ / READA / ILLEGAL (*1) WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS DESEL NOP ILLEGAL (*1) ILLEGAL (*1) / ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRFC) NOP (Idle after tRFC)
READ / READA / ILLEGAL WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS DESEL NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tMRD) NOP (Idle after tMRD)
READ / READA / ILLEGAL WRITE / WRITEA Active PRE / PREA Refresh MRS / EMRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
H = High Level, L = Low level, X = Don't Care BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation ILLEGAL = Device operation and / or data integrity are not guaranteed. Note : 1. 2. 3. 4. 5. 6. This command may be issued for other banks, depending on the state of the banks. All banks must be in "IDLE". All AC timing specs must be met. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings is illegal. Available in case tRCD is satisfied by AL setting. Available in case tWTR is satisfied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009 Revision : 1.1 55/59
ESMT
Simplified States Diagram
Power-Up and Initialization Sequence
M14D2561616A
CKEL
OCD calibration PR Idle Settign MRS EMRS (E)MRS All banks precharged CKEL ACT CKEH SRF CKEH
Self Refreshing
REF
Refreshing
CKEL Precharge PowerDown CKEL
CKEL Active Power -Down
CKEL
Activating Automatic Sequence Command Sequence
CKEH CKEL Bank Active Write Write WRA Write RDA Read Write Reading Read Read
WRA WRA Writing With Auto Precharge PR, PRA RDA PR, PRA PR, PRA
RDA
Reading With Auto Precharge
Precharging
CKEL = CKE LOW CKEH = CKE HIGH ACT = Activate WR(A) = Write (with Auto Precharge) RD(A) = Read (with Auto Precharge) PR(A) = Precharge (All) (E)MRS = (Extended) Mode Register Set SRF = Enter Self Refresh REF = Auto Refresh
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009 Revision : 1.1 56/59
ESMT
PACKING 84-BALL DIMENSIONS DDR SDRAM ( 10x12.5 mm )
M14D2561616A
Symbol A A1 b D E D1 E1 e e1
Dimension in mm Min Norm Max 1.20 0.30 0.35 0.40 0.40 0.45 0.50 9.90 10.00 10.10 12.40 12.50 12.60 6.40 BSC 11.20 BSC 0.80 BSC 0.80 BSC
Dimension in inch Min Norm Max 0.047 0.012 0.014 0.016 0.016 0.018 0.020 0.390 0.394 0.398 0.488 0.492 0.496 0.252 BSC 0.441 BSC 0.031 BSC 0.031 BSC
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009 Revision : 1.1 57/59
ESMT
Revision History
Revision 0.1 0.2 Date 2008.02.25 2008.03.11 Original Description
M14D2561616A
0.3 1.0 1.1
2008.04.30 2009.02.06 2009.02.27
1. Delete -3.75 and -5 speed grade 2. Add 3.9us refresh interval at +85C < Tc +95C 3. Modify DC spec 4. Add CL6 1. Add VOH, VOL and AC overshoot/ undershoot spec. 2. Add notes for AC operation test condition and AC timing parameter & specification. 3. Add clock jitter and input slew rate spec. 1.Delete "Preliminary" 2.Move Revision History to the last Correct the marking for e1 of packing dimension
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009 Revision : 1.1 58/59
ESMT
Important Notice All rights reserved.
M14D2561616A
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009 Revision : 1.1 59/59

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